In an existing High Speed Serializer/Deserializer (SERDES) system, circuits for synchronous sampling in-phase/quadrature (I/Q) signal groups under high-speed interface face challenges in aspects of layout and design.
Although an independent frequency divider can be used to separately divide in-phase/quadrature clock signals to independently control timing of the individual signals, frequency division results can yield several different results based on a reset state of the frequency divider and relationships between the in-phase/quadrature signal groups.
For example, supposing that the conventional frequency divider starts frequency division for rising edges of the clock signal. Regarding a relationship between the reset signal and the in-phase/quadrature clock signal group, if the in-phase/quadrature clock signals sequentially appear after the rising edge trigger point of the reset signal, the result of the frequency division will be maintained in a relationship where the in-phase clock signal leads the quadrature clock signal by 90 degrees. On the other hand, if the rising edge trigger point of the reset signal appears exactly between a rising edge of the in-phase clock signal and a rising edge of the quadrature clock signal, the result of the frequency division for the quadrature clock signal would lead that for the in-phase clock signal, causing the phase of the in-phase clock signal to fall behind the phase of the quadrature clock signal by 90 degrees. Such issues can cause disorders for the timing when the circuits use the results of the frequency division for the in-phase/quadrature clock signals.
Therefore, improving circuit designs to ensure a sequence of the in-phase/quadrature clock signal group and a correct sampling relationship for the clock signals, while avoiding the disorders for the timings of the in-phase/quadrature clock signal group, has become an important issue in the art.